1. Field of the Invention
The present invention generally relates to semiconductor devices. More particularly, the present invention relates to the electrically coupling a pad metal layer and a lower metal layer in a semiconductor device.
2. Related Art
The semiconductor fabrication process generally includes a probing process. In the probing process, a probe instrument is utilized to make mechanical and electrical contact with the exposed surface of the pad metal of an integrated circuit chip (or die). Voltage or current is then applied through the probe instrument to test for functionality. Unfortunately, the probe instrument may induce stress on the pad metal such that the stress propagates to lower layers of the integrated circuit chip. As a result, a layer(s), such as an interlayer dielectric between metal layers, can crack and become damaged, leading to reliability problems. Similarly, the wire-bonding process can cause cracking and damage to a layer(s) of the integrated circuit chip.
FIG. 1A illustrates a cross-sectional view of a semiconductor structure 100 of a conventional integrated circuit chip. As shown in FIG. 1A, the semiconductor structure 100 includes a pad metal layer 10 having an exposed surface 12, an interlayer dielectric (ILD) 40, and a lower metal layer 20. Moreover, the semiconductor structure 100 further includes an insulating dielectric 30 that covers the perimeter area of the pad metal layer 10. Additionally, the semiconductor structure 100 includes a plurality of vias 25 formed in the interlayer dielectric (ILD) 40 to electrically couple the pad metal layer 10 and the lower metal layer 20. As depicted in FIG. 1A, the vias 25 are formed below the exposed surface 12 of the pad metal layer 10. This illustrates how the stress, induced by the probe instrument, propagates to lower layers of the integrated circuit chip through the vias 25.
A top view of the semiconductor structure 100 of the conventional integrated circuit chip of FIG. 1A is shown in FIG. 1B. The top view of FIG. 1B depicts the insulating dielectric 30 and the exposed surface 12 of the pad metal layer 10. Moreover, the symbols 60 illustrate the position of the vias 25 below the pad metal layer 10.